1. Field of the Invention
The present invention relates to a multi-screen synthesis apparatus that controls a unified memory included, e.g., in a digital TV receiver having a multi-screen display function, and a control method and control program for controlling the multi-screen synthesis apparatus.
2. Description of the Related Art
Nowadays, in the broadcasting industry, a shift from analog ground wave broadcasting to BS/CS digital broadcasting, i.e., so-called “digitalization of broadcasting,” is proceeding. With the progress of this shift, there is a rising trend of change in the role of a TV set from “amusement means in a living room” to “home information window”. This trend toward digitalization of broadcasting causes an increase in the number of programs transmitted to homes (multi-channeling) and enhancement in definition or resolution (increase in transmitted information) from SD (Standard Definition) to HD (High Definition).
In this movement, the role of a display device is also changing. More specifically, the display device tends to have a larger and higher definition screen so as to express realistic pictures full of presence in a living room of a home. A typical example is, e.g., a PDP (plasma display) of over 50 inches. Conventionally, demands for the display devices of this class have been limited to those for business uses in public facilities. However, it is now expected that with reduction of manufacturing costs in the future, they will be also used in homes. Further, it is inevitable that a receiver (set top box) having higher performance will have to be produced at lower costs.
In accordance with the above-mentioned digitalization of broadcasting and use of large-sized and enhanced-definition display devices, the expectation is that a display mode called “multi-screen display” which enables simultaneous display of various media on a single display device serves as one of means for making a TV set the “home information window”.
Some recent TV receivers are already equipped with a function of receiving programs over two channels simultaneously and displaying these simultaneously on a display screen, and there is a high possibility that the number of screens or windows displayed on the display screen will increase depending on the purposes of watching TV.
Further, with digitalization of broadcasting, TV broadcasting has come to serve not only as means for simply transmitting video images in only one direction, but also as means for enabling interactive communication between each user and a broadcasting station. A typical example of this type of broadcasting is data broadcasting.
The data broadcasting is achieved by developing a teletext broadcasting system employed by the conventional analog broadcast, in which a TV station provides information to viewers in one way only, into an advanced system in which new services, such as interactive and on-demand type multi-media services, are added. Various broadcast services typified by program-interlocking services, EPG (Electronic Program Guide) services, e-commerce, and data distribution, are now being considered for data broadcasting.
The data broadcasting is standardized by the Association of Radio Industries and Businesses (ARIB) in Japan, and details of the standardized data broadcasting are described in an ARIB standard document (ARIB STD B-24: Specification of Data Coding System and Transmission System for Digital Broadcasting). This standard stipulates a requirement that the receiver should have a display capability of smoothly synthesizing graphical user interface (GUI), similarly to the personal computer. It is also required that the GUI display should be capable of displaying not only the above-mentioned data broadcasting, but also GUI screens, on an as-needed basis, for operation support enabling easy control of various devices (a digital camera, a digital video tape recorder, a DVD recorder or player, a DVHS deck, etc.) connected to a TV, from the TV side.
From the above-mentioned background, it is desired to realize in the future a home-use receiver which is capable of performing simultaneous display of a plurality of broadcast video screens and video images from a peripheral device or apparatus, on a multi-screen without causing a viewer to feel a sense of incongruity, and smoothly displaying graphics of a GUI screen of a data broadcast, a user interface (Ul), or the like, without causing the viewer to feel a sense of incongruity. Further, it is desired to realize these display functions at low costs.
One conventional method to realize the multi-screen display functions mentioned above is to temporally store input sources different in frame rate in a memory, and then read them from the memory in synchronism with a fresh rate of a display device, for synthesized output. It is known that in this case a control method is employed in which a frame memory is controlled as a unified memory using the UMA (Unified Memory Architecture), so as to reduce system costs.
In this case, a transfer rate demanded of the frame memory (memory transfer rate) is generally determined by a method of calculating the same based on a total of all simultaneously available transfer rates, by using the following inequality (1):memory transfer rate>Σ(input rate)+Σ(output rate)  (1)
However, in a digital television having the multi-screen display function, if its memory transfer rate is determined based on the total of all transfer rates, the frequency of a memory transfer clock becomes very high.
Detailed explanation of this will be given below (only as one example).
First, parameters necessary for estimating transfer capacity are set as follows:
HD video input (YcbCr444): 24 bits, 75 MHz (1)
HD video output (YcbCr444): 24 bits, 75 MHz (2)
OSD image (YcbCr444): 24 bits, 75 MHz (3)
OSD image (INDEX color): 8 bits, 75 MHz (4)
The above requirement (1) is for inputting a hi-vision video.
The above requirement (2) is for outputting a hi-vision video.
The above parameter (3) is for drawing an OSD image in a still picture plane for data broadcasting.
The above requirement (4) is for drawing an OSD image in text & graphic and subtitle planes for data broadcasting.
(1) When a two-screen multi-window is formed by two channels of video inputs and three channels of OSD images, a unified memory is reserved for the following planes:
moving picture plane 0 (from (1) parameters): 1280×720×24
moving picture plane 1 (from (1) parameters): 1280×720×24
OSD plane 0 (from (3) parameters): 1280×720×24
(This plane corresponding to a still picture plane in the ARIB specification.)
OSD plane 1 (from (4) parameters): 640×360×8
(This plane corresponds to a text & graphic plane in the ARIB specification.)
OSD plane 2 (from (4) parameters): 640×360×8
(This plane corresponds to a subtitle plane in the ARIB specification.)
Specifications required of the unified memory are calculated as follows:
                                                        ∑                              (                                  maximum                  ⁢                                                                          ⁢                  input                  ⁢                                                                          ⁢                  rate                                )                                      =                          (                              transfer                ⁢                                                                  ⁢                capacity                ⁢                                                                  ⁢                of                ⁢                                                                  ⁢                                  (                  1                  )                                            )                                )                ×        2            +              transfer        ⁢                                  ⁢        capacity        ⁢                                  ⁢                  of          ⁡                      (            3            )                              +                        (                      transfer            ⁢                                                  ⁢            capacity            ⁢                                                  ⁢                          of              ⁡                              (                4                )                                              )                ×        2              =                                        (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    ×          2                +                  (                      24            ⁢                                                  ⁢            bits            ×            75            ⁢                                                  ⁢                          MHz              ÷              8                                )                +                              (                          8              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    ×          2                    =                                    450            ⁢                                                  ⁢                          MB              /              S                                +                      225            ⁢                                                  ⁢                          MB              /              S                                +                      150            ⁢                                                  ⁢                          MB              /              S                                      =                  825          ⁢                                          ⁢                      MB            /            S                                          ∑              (                  maximum          ⁢                                          ⁢          output          ⁢                                          ⁢          rate                )              =                            (                      transfer            ⁢                                                  ⁢            capacity            ⁢                                                  ⁢            of            ⁢                                                  ⁢                          (              2              )                                )                +                  transfer          ⁢                                          ⁢          capacity          ⁢                                          ⁢                      of            ⁡                          (              3              )                                      +                              (                          transfer              ⁢                                                          ⁢              capacity              ⁢                                                          ⁢                              of                ⁡                                  (                  4                  )                                                      )                    ×          2                    =                                    (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    +                      (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    +                                    (                              8                ⁢                                                                  ⁢                bits                ×                75                ⁢                                                                  ⁢                                  MHz                  ÷                  8                                            )                        ×            2                          =                                            225              ⁢                                                          ⁢                              MB                /                S                                      ⁢                                                  +                                                  ⁢                          225              ⁢                                                          ⁢                              MB                /                S                                      ⁢                                                  +                                                  ⁢                          150              ⁢                                                          ⁢                              MB                /                S                                              ⁢                                          =                      600            ⁢                                                  ⁢                          MB              /              S                                                      Required      ⁢                          ⁢      memory      ⁢                          ⁢      bandwidth        =                            ∑                      (                          maximum              ⁢                                                          ⁢              input              ⁢                                                          ⁢              rate                        )                          +                  ∑                      (                          maximum              ⁢                                                          ⁢              output              ⁢                                                          ⁢              rate                        )                              =                                    825            ⁢                                                  ⁢                          MB              /              S                                +                      600            ⁢                                                  ⁢                          MB              /              S                                      =                  1425          ⁢                                          ⁢                      MB            /            S                              
Assuming that the transfer efficiency of the memory is 65%, the following equations are obtained:effective memory bandwidth=required memory bandwidth×(100÷65)≈2.2 GB/Srequired memory capacity≈8.56 MB.
(2) When a four-screen multi-window is formed by four channels of video inputs of and three channels of OSD images, a unified memory is reserved for the following planes:
moving picture plane 0 (from (1) parameters): 1280×720×24
moving picture plane 1 (from (1) parameters): 1280×720×24
moving picture plane 2 (from (1) parameters): 1280×720×24
moving picture plane 3 (from (1) parameters): 1280×720×24
OSD plane 0 (from (3) parameters): 1280×720×24
(This plane corresponding to a still picture plane in the ARIB specification.)
OSD plane 1 (from (4) parameters): 640×360×8
(This plane corresponds to a text & graphic plane in the ARIB specification.)
OSD plane 2 (from (4) parameters): 640×360×8
(This plane corresponds to a subtitle plane in the ARIB specification.)
Specifications required of the unified memory are calculated as follows:
            ∑              (                  maximum          ⁢                                          ⁢          input          ⁢                                          ⁢          rate                )              =                                        (                          transfer              ⁢                                                          ⁢              capacity              ⁢                                                          ⁢              of              ⁢                                                          ⁢                              (                1                )                                      )                    ×          4                +                  transfer          ⁢                                          ⁢          capacity          ⁢                                          ⁢                      of            ⁡                          (              3              )                                      +                              (                          transfer              ⁢                                                          ⁢              capacity              ⁢                                                          ⁢                              of                ⁡                                  (                  4                  )                                                      )                    ×          2                    =                                                  (                              24                ⁢                                                                  ⁢                bits                ×                75                ⁢                                                                  ⁢                                  MHz                  ÷                  8                                            )                        ×            4                    +                      (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    +                                    (                              8                ⁢                                                                  ⁢                bits                ×                75                ⁢                                                                  ⁢                                  MHz                  ÷                  8                                            )                        ×            2                          =                                            900              ⁢                                                          ⁢                              MB                /                S                                      +                          225              ⁢                                                          ⁢                              MB                /                S                                      ⁢                                                  +                                                  ⁢                          150              ⁢                                                          ⁢                              MB                /                S                                              ⁢                                          =                                          ⁢                      1275            ⁢                                                  ⁢                          MB              /              S                                                      ∑              (                  maximum          ⁢                                          ⁢          output          ⁢                                          ⁢          rate                )              =                            (                      transfer            ⁢                                                  ⁢            capacity            ⁢                                                  ⁢            of            ⁢                                                  ⁢                          (              2              )                                )                +                  transfer          ⁢                                          ⁢          capacity          ⁢                                          ⁢                      of            ⁡                          (              3              )                                      +                              (                          transfer              ⁢                                                          ⁢              capacity              ⁢                                                          ⁢                              of                ⁡                                  (                  4                  )                                                      )                    ×          2                    =                                    (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    +                      (                          24              ⁢                                                          ⁢              bits              ×              75              ⁢                                                          ⁢                              MHz                ÷                8                                      )                    +                                    (                              8                ⁢                                                                  ⁢                bits                ×                75                ⁢                                                                  ⁢                                  MHz                  ÷                  8                                            )                        ×            2                          =                                            225              ⁢                                                          ⁢                              MB                /                S                                      +                          225              ⁢                                                          ⁢                              MB                /                S                                      +                          150              ⁢                                                          ⁢                              MB                /                S                                              =                      600            ⁢                                                  ⁢                          MB              /              S                                                      Required      ⁢                          ⁢      memory      ⁢                          ⁢      bandwidth        =                            ∑                      (                          maximum              ⁢                                                          ⁢              input              ⁢                                                          ⁢              rate                        )                          +                  ∑                      (                          maximum              ⁢                                                          ⁢              output              ⁢                                                          ⁢              rate                        )                              =                                    1275            ⁢                                                  ⁢                          MB              /              S                                ⁢                                          +                                          ⁢                      600            ⁢                                                  ⁢                          MB              /              S                                      ⁢                                  =                                  ⁢                  1875          ⁢                                          ⁢                      MB            /            S                              
Assuming that the transfer efficiency of the memory is 65%, the following equations are obtained:effective memory bandwidth=required memory bandwidth×(100÷65)≈2.9 GB/Srequired memory capacity ≈14 MB
The above results show that in any one of the conditions (1) and (2), the required memory capacity does not affect system costs. This is because with recent development in DRAM processing technique, memory capacity has been increased, and even a memory with the smallest capacity has more than 128 MB per chip.
However, the transfer rate has a great effect on system costs in both of the cases of the conditions (1) and (2), because the required memory bandwidth is approximately from 2 GB/S to 3 GB/S.
In fact, when a DRAM configuration using ×32-bit width DDR-SDRAM's having an operating frequency of 200 MHz (the maximum transfer rate of 800 MB/S) and capable of processing the above required memory bandwidth, is estimated, the case (1) necessitates the use of three DDR-SDRAM chips, and the case (3) necessitates the use of four DDR-SDRAM chips.
Almost the same goes for a RDRAM.
In short, an increased number of memories are needed, and this increases system costs.
Further, there is a high possibility that research and development conducted in various ways will increase the transfer rate of a memory in the future. However, under the present circumstances, to increase the memory transfer rate is not so easy as to increase the memory capacity, when taking physical conditions for transfer, including a circuit board, into consideration.
To solve the above problem, beside the above described method of determining a required memory bandwidth in view of a maximum transfer rate of input and output, there has been proposed a method of writing into an OSD plane during each blank period of a horizontal or vertical synchronizing signal.
During the blank period, access to a moving picture plane is interrupted, and hence, it is possible to estimate a required memory bandwidth by removing a bandwidth for access to the OSD plane. Therefore, in the above example, the required bandwidth can be reduced as follows in each of the cases (1) and (2):
(1) 2.2 GB/S to 1.8 GB/S
(2) 2.9 GB/S to 2.5 GB/S
However, according to this method, since processing of data of video sources is executed preferentially, when the number of screens or windows to be displayed on a multi-screen is increased, it is probable that OSD (GUI) drawing wait time will increase.
Particularly when a GUI screen, e.g., by data broadcasting, is to be drawn with acceleration, or when the stream-based data of a moving picture, e.g., of MPEG4, becomes an element of a GUI screen in the future, the above problem becomes a serious one, causing a user to visually notice a sense of incongruity during updating of the data, which can subject the user to a kind of stress.
To address this problem, there is another method of drawing an OSD image preferentially and limiting the number of screens that can be displayed simultaneously on a multi-screen during the OSD image. However, this method is not favorable to development in applications using a multi-screen since the degree of freedom is lost.
Therefore, there is a strong demand for a memory control method which gives a solution to this dilemma of meeting contradictory requirements, and contributes to reduction of system costs.